This invention relates to semiconductor manufacture and to methods for testing the operability of unpackaged semiconductor dice having raised or bumped bond pads. In addition, this invention relates to methods for fabricating an interconnect suitable for testing the operability of integrated circuitry on an unpackaged semiconductor die formed with raised or bumped bond pads.
Because of a trend towards multi-chip modules, semiconductor manufacturers are required to supply unpackaged dice that have been tested and certified as known good die (KGD). Known good die is a collective term that denotes unpackaged die having the same reliability as the equivalent packaged die.
The need for known good die has led to the development of test apparatus in the form of temporary carriers suitable for testing discrete, unpackaged semiconductor dice. As an example, test apparatus for conducting burn-in tests for discrete die are disclosed in U.S. Pat. No. 4,899,107 to Corbett et al. and U.S. Pat. No. 5,302,891 to Wood et al., which are assigned to Micron Technology, Inc. Other test apparatus for discrete die are disclosed in U.S. Pat. No. 5,123,850 to Elder et al., and U.S. Pat. No. 5,073,117 to Malhi et al., which are assigned to Texas Instruments.
With this type of test apparatus, a non-permanent electrical connection must be made between contact locations on the die, such as bond pads, and external test circuitry associated with the test apparatus. The bond pads provide a connection point for testing the integrated circuitry formed on the die.
In making this temporary electrical connection, it is desirable to effect a connection that causes as little damage as possible to the bond pad. If the temporary connection to a bond pad damages the pad, the entire die may be rendered as unusable. This is difficult to accomplish because the connection must also produce a low resistance or ohmic contact with the bond pad. A bond pad typically includes a metal oxide layer that must be penetrated to make an ohmic contact.
Some prior art contact structures, such as probe cards, scrape the bond pads which wipes away the oxide layer and causes excessive damage to the bond pads. Other interconnect structures such as probe tips may pierce both the oxide layer and the metal bond pad and leave a deep gouge. Still other interconnect structures, such as microbumps, may not even pierce the oxide layer preventing the formation of an ohmic contact.
Another important consideration in testing of known good die is the effect of thermal expansion during the test procedure. As an example, during burn-in testing, a die is heated to an elevated temperature and maintained at temperature for a prolonged period. This causes thermal expansion of the die and temporary interconnect. If the die and the temporary interconnect expand by a different amount, stress may develop at the connection point and adversely effect the electrical connection. This may also lead to excessive damage of bond pads.
One type of semiconductor dice having a raised topology is referred to as a xe2x80x9cbumpedxe2x80x9d die. A xe2x80x9cbumpedxe2x80x9d semiconductor die includes bond pads formed with a bump of solderable material such as a lead-tin alloy. Bumped dice are often used for flip chip bonding wherein the die is mounted face down on a substrate, such as a printed circuit board, and then attached to the substrate by welding or soldering. Typically the bumps are formed as balls of material that are circular in a cross sectional plane parallel to the face of the die. The bumps typically have a diameter of from 50 xcexcm to 100 xcexcm. The sides of the bump typically bow or curve outwardly from a flat top surface. The flat top surface forms the actual region of contact with a mating electrode on the printed circuit board or other substrate.
In the past, following testing of a bumped die, it has been necessary to reflow the bumps, which are typically damaged by the test procedure. This is an additional process step which adds to the expense and complexity of the testing process. Furthermore, it requires heating the tested die which can adversely affect the integrated circuitry formed on the die.
In view of the need in the art for improved methods for testing unpackaged, bumped, semiconductor dice, it is an object of the present invention to provide an improved method of testing unpackaged semiconductor dice having raised or bumped bond pads.
It is a further object of the present invention to provide an improved method for forming a temporary interconnect adapted to test semiconductor die having raised or bumped bond pads.
It is a further object of the present invention to provide an improved method for fabricating temporary interconnects for bumped semiconductor dice that uses semiconductor manufacturing techniques and that provides an improved contact structure.
Other objects, advantages and capabilities of the present invention will become more apparent as the description proceeds.
In accordance with the present invention, an improved method of testing, and an improved method for fabricating a temporary interconnect for testing unpackaged semiconductor dice having raised contact locations (e.g., bumped bond pads) are provided. The improved method of testing includes a temporary interconnect adapted to establish an electrical connection with raised contact locations on the die without damage to the contact locations. The interconnect includes a substrate (e.g., silicon) having contact members formed in a pattern that matches the size and spacing of the contact locations on the die. The contact members on the interconnect include one or more sharpened projections. The sharpened projections are adapted to penetrate the raised contact locations on the die and to pierce any residual insulating material to establish an ohmic connection.
The sharpened projections are formed integrally with the substrate using an etching process or using an oxidation growth process. The sharpened projections are formed either on a surface of the substrate, or in a recess in the substrate which is sized to retain the raised contact locations on the die. In addition, the sharpened projections are formed with a size and shape which permits penetration into the contact locations but with a self-limiting penetration depth. In an illustrative embodiment, the sharpened projections are formed as an array of parallel elongated blades. Depending on the method of formation, the elongated blades can be formed in a variety of cross sectional configurations (e.g., triangular, rounded profile, flat tops). In addition, the elongated blades can be formed in a spaced array or with no spaces therebetween.
The sharpened projections are formed on an insulating layer of the interconnect substrate and are covered with a conductive layer. The conductive layer can be formed as a single layer of a highly conductive metal such as aluminum or iridium, or a conductive material such as polysilicon. Conductive traces or runners are formed in electrical contact with the conductive layer to establish an electrical pathway to and from the contact members of the interconnect.
The conductive layer for the contact members can also be formed as a stack comprising two different layers of material. An outer layer of the stack is preferably a metal such as platinum, which is chemically inert and provides a barrier layer that will not react with the raised material (e.g., bump) at the contact location on the die. The inner layer of the stack can be a metal such as aluminum or titanium which can be easily bonded to conductive traces. The inner layer and conductive traces can also be formed of a same material.
The conductive layer can also be formed as a metal silicide. A metal silicide can be formed by depositing a silicon containing layer and a metal layer on the sharpened projections and reacting these layers to form a metal silicide. The unreacted portions of the silicon containing layer and metal layer are then etched selective to the metal silicide using a salicide process.
A method for fabricating a temporary interconnect in accordance with the invention, includes the steps of: forming a substrate; forming an array of contact members on the substrate as one or more elongated sharpened projections adapted to penetrate a raised contact location (e.g., bump) on a die to a limited penetration depth; forming an insulating layer (e.g., SiO2, Si3N4) over the entire substrate including the sharpened projections; forming a conductive layer over the sharpened projections; and then forming conductive traces on the substrate in electrical communication with the conductive layer. Optionally, the sharpened projections can be mounted within an indentation formed in the substrate that is adapted to retain the raised contact location on the die.
Preferably a large number of interconnects are formed on a single substrate or wafer. This substrate can then be diced (e.g., saw cut) to singulate the interconnects. In use, the temporary interconnect is placed in a temporary carrier (i.e., test apparatus) along with the die, and an electrical path is established between the conductive traces on the interconnect and external test circuitry associated with the test apparatus.